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Journal articles

YEARAUTHORS TITLEJOURNALISSUE PDF * BIBTEX
2013M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian, B. Becker SAT-based Analysis of Sensitisable Paths D&T to appear n/a BibTeX
2010A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, B. Becker Thread-parallel integrated test pattern generator utilizing satisfiability analysis IJPP 38(3-4): Jun 2010 Springer Online First BibTeX
2007I. Polian, A. Czutro, S. Kundu, B. Becker Power Droop Testing D&T 24(3): May/Jun 2007 IEEEXplore BibTeX

Papers in formal proceedings (refereed)

YEARAUTHORS TITLECONFERENCE PDF * BIBTEX
2014M. Sauer, I. Polian, M.E. Imhof, A. Mumtaz, E. Schneider, A. Czutro, H.-J. Wunderlich, B. Becker Variation-Aware Deterministic ATPG ETS to appear BibTeX
2014A. Czutro, I. Polian, S.M. Reddy, B. Becker SAT-Based Test Pattern Generation with Improved Dynamic Compaction VLSI Design to appear BibTeX
2012 A. Czutro, M. Imhof, J. Jiang, A. Mumtaz, M. Sauer, B. Becker, I. Polian and H.-J. Wunderlich Variation-Aware Fault Grading ATS n/a BibTeX
2012 M. Sauer, A. Czutro, I. Polian and B. Becker Small-Delay-Fault ATPG with Waveform Accuracy ICCAD n/a BibTeX
2012 M. Sauer, S. Kupferschmid, A. Czutro, I. Polian, S.M. Reddy and B. Becker Functional Test of Small-Delay Faults using SAT and Craig Interpolation ITC n/a BibTeX
2012 L. Feiten, M. Sauer, T. Schubert, A. Czutro, E. Böhl, I. Polian and B. Becker #SAT-based Vulnerability Analysis of Security Components – A Case Study DFT n/a BibTeX
2012 A. Czutro, M. Sauer, I. Polian and B. Becker Multi-Conditional SAT-ATPG for Power-Droop Testing ETS IEEE; local copy; slides BibTeX
2012 M. Sauer, A. Czutro, B. Becker and I. Polian On the Quality of Test Vectors for Post-Silicon Characterization ETS IEEE; local copy BibTeX
2012 A. Czutro, M. Sauer, T. Schubert, I. Polian and B. Becker SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms VTS IEEE; local copy; slides BibTeX
2012 J. Jiang, M. Sauer, A. Czutro, B. Becker and I. Polian On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints DATE IEEE BibTeX
2012M. Sauer, S. Kupferschmid, A. Czutro, S.M. Reddy, B. Becker Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation VLSI Design IEEE; local copy BibTeX
2011M. Sauer, J. Jiang, A. Czutro, I. Polian, B. Becker Efficient SAT-Based Search for Longest Sensitisable Paths ATS IEEE; local copy BibTeX
2011M. Sauer, A. Czutro, I. Polian, B. Becker Estimation of Component Criticality in Early Design Steps IOLTS IEEE; local copy BibTeX
2011M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian, B. Becker SAT-based analysis of sensitisable paths
(Best Paper Award in the Test Category)
DDECS IEEE; local copy BibTeX
2009A. Czutro, I. Polian, P. Engelke, S.M. Reddy, B. Becker Dynamic Compaction in SAT-Based ATPG ATS IEEE; local copy; slides BibTeX
2009M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker ATPG-Based Grading of Strong Fault-Secureness IOLTS IEEE BibTeX
2009N. Houarche, A. Czutro, M. Comte, P. Engelke, I. Polian, B. Becker, M. Renovell An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects VTS IEEE BibTeX
2009A. Czutro, I. Polian, M. Lewis, P. Engelke, S.M. Reddy, B. Becker TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis VLSI Design IEEE; local copy; slides BibTeX
2008A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, B. Becker A Simulator of Small-Delay Faults Caused by Resistive-Open Defects ETS IEEE; local copy; slides BibTeX
2006I. Polian, A. Czutro, S. Kundu, B. Becker Power droop testing ICCD IEEE; local copy BibTeX
2005I. Polian, A. Czutro, B. Becker Evolutionary optimization in code-based test compression DATE IEEE; local copy; slides BibTeX

Workshop contributions (refereed)

YEARAUTHORS TITLEWORKSHOP PDF * BIBTEX
2013 L. Feiten, M. Sauer, T. Schubert, A. Czutro, V. Tomashevich, E. Böhl, I. Polian and B. Becker #SAT-based Vulnerability Analysis of Security Components ETS n/a BibTeX
2012 A. Czutro, M. Sauer, I. Polian, B. Becker Multi-Conditional ATPG using SAT with Preferences GI/GMM/ITG TuZ local copy; slides BibTeX
2012 M. Sauer, S. Kupferschmid, A. Czutro, I. Polian, S. Reddy and B. Becker Functional Justification in Sequential Circuits using SAT and Craig Interpolation GI/GMM/ITG TuZ local copy BibTeX
2011 J. Jiang, M. Sauer, A. Czutro, B. Becker and I. Polian On the Optimality of K Longest Path Generation IEEE Workshop on RTL and High Level Testing n/a BibTeX
2009 A. Czutro, B. Becker and I. Polian Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures IEEE East-West Design & Test Symposium local copy; slides BibTeX
2009M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung ZuE n/a BibTeX
2009 A. Czutro, B. Becker and I. Polian Performance Evaluation of SAT-Based Automatic Test Pattern Generation on Multi-Core Architectures Many-Cores Workshop ARCS local copy; slides BibTeX
2009N. Houarche, A. Czutro, M. Comte, P. Engelke, I. Polian, B. Becker, M. Renovell Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects LATW n/a BibTeX
2009 A. Czutro, B. Becker and I. Polian Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures (poster) GI/GMM/ITG TuZ local copy; poster BibTeX
2008 A. Czutro, I. Polian, M. Lewis, P. Engelke, S.M. Reddy, B. Becker TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis (poster) EDA local copy; poster BibTeX
2004I. Polian, B. Becker, A. Czutro Compression methods for path delay fault test pair sets: a comparative study (poster) ETS local copy BibTeX

Invited and misc. presentations

DATEEVENT HOSTTITLE PDF *
March 2012 South European Test Seminar, Sauze d'Oulx, Italy n/a ATPG for Complex Defect Mechanisms Using SAT with Preferences slides
March 2011 South European Test Seminar, Montchavin, France n/a Estimation of Component Criticality by Means of Statistical Delay Fault Simulation slides
March 2010 South European Test Seminar, St. Leonhard, Austria n/a New developments in SAT-based ATPG slides
May 2009 ETS Student's Forum, Sevilla, Spain n/a Improving SAT-based ATPG slides; poster
March 2009 South European Test Seminar, Valmorel, France n/a Improving SAT-based ATPG slides
March 2008 South European Test Seminar, Obergurgl, Austria n/a A Simulator of Small-Delay Faults Caused by Resistive-Open Defects slides
March 2006 South European Test Seminar, Neustift im Stubaital, Austria n/a Power Droop Testing slides
November 2005 Freiburg-Paderborn-Stuttgart-Workshop, Freudenstadt, Germany n/a Power Droop Testing slides
March 2005 South European Test Seminar, St. Leonhard, Austria n/a Evolutionary Optimization in Code-Based Test Compression slides
December 2004 Freiburg-Innsbruck-Stuttgart-Workshop, Obergurgl, Austria n/a Evolutionary Optimization in Code-Based Test Compression slides

Monographs

DATE TYPE TITLE PDF
August 2013 Doctoral Thesis Efficiency and Applications of SAT-Based Test Pattern Generation — Complex fault models and optimisation problems Amazon
April 2007 Degree Thesis (“Diplomarbeit”) Simulation of Dynamic Effects of Resistive Open Defects local copy
February 2006 Minor Thesis (“Studienarbeit”) Automatic Test Pattern Generation for Power Droop Testing local copy


* Please use the version stored on the copyright holder's server whenever possible. The local copies are for educational and research use only. No guarantees are made regarding the local copies.

Design by Alexander Czutro